Timed Chi: Modeling, Simulation and Verification of Hardware Systems

Timed Chi (chi) is a timed process algebra, designed for Modeling, simulation, verification and real-time control. Its application domain consists of large and complex manufacturing systems. The straightforward syntax and semantics are also highly suited to architects, engineers and researchers from the hardware design community. There are many different tools for timed Chi that support the analysis and manipulation of timed Chi specifications; and such tools are the results of software engineering research with a very strong foundation in formal theories/methods. Since timed Chi is a well-developed algebraic theory from the field of process algebras with timing, we have the idea that timed Chi is also well-suited for addressing various aspects of hardware systems (discrete-time systems by nature). To show that timed Chi is useful for the formal specification and analysis of hardware systems, we illustrate the use of timed Chi with several benchmark examples of hardware systems

Students\u27 perception on the use of visual tilings to support their learning of programming concepts

In this research, we explore the use of visual tiling patterns (tilings for short) in the teaching of basic programming concepts to novice students. Tilings are made by connecting regular polygons side-by-side and their construction can be defined by the use of a simple set of commands. We believe tilings are a suitable context to situate the learning of elementary programming concepts for beginning programmers. The importance of placing commands in a proper sequence, of grouping a set of commands and using them repetitively, and of identifying logical errors can be demonstrated using tilings. We have created a prototype, which allows learners to create tilings based on a simple textual language, and used it within an introductory programming class at a Chinese university, where most students have minimal or no programming experience. After using the prototype in class, we conducted a class survey asking students about their perception of the usefulness of such the tool to support their learning. In this paper, we report the findings and our experiences using the tool. © 2013 IEEE

Binomial American Option Pricing on CPU-GPU Hetergenous System

Abstract-We present a novel parallel binomial algorithm to compute prices of American options. The algorithm partitions a binomial tree into blocks of multiple levels of nodes, and assigns each such block to multiple processors. Each processor in parallel with the others computes the option's values at nodes assigned to it. The computation consists of two phases, where the second phase can not start until the valuation in the first phase has been completed. The algorithm is implemented and tested on a heterogeneous system consisting of an Intel multicore processor and a NVIDIA GPU. The whole task is split and divided over the CPU and GPU so that the computations are performed on the two processors simultaneously. In the hybrid processing, the GPU is always assigned the last part of a block, and makes use of a couple of buffers in the on-chip shared memory to reduce the number of accesses to the off-chip device memory. The performance of the hybrid processing is compared with an optimised CPU serial code, a CPU parallel implementation and a GPU standalone program. We learned from the experiments that the lack of explicit mechanism in CUDA for synchronising CPU and GPU executions is a major obstacle for the hybrid processing to achieve high performance

Monocular line tracking for the reduction of vibration induced during image acquisition

This article details our research in the use of monocular cameras mounted on moving vehicles such as quadcopter or similar unmanned aerial vehicles (UAV). These cameras are subjected to vibration due to the constant movement experienced by these vehicles and consequently the captured images are often distorted. Our approach uses the Hough transform for line detection but this can be hampered when the surface of the objects to be captured has a high reflection factor. Our approach combines two key algorithms to detect and reduce both glare and vibration induced during image acquisition from a moving object

Collaborative behavior, performance and engagement with visual analytics tasks using mobile devices

Interactive visualizations are external tools that can support users’ exploratory activities. Collaboration can bring benefits to the exploration of visual representations or visu‐ alizations. This research investigates the use of co‐located collaborative visualizations in mobile devices, how users working with two different modes of interaction and view (Shared or Non‐Shared) and how being placed at various position arrangements (Corner‐to‐Corner, Face‐to‐Face, and Side‐by‐Side) affect their knowledge acquisition, engagement level, and learning efficiency. A user study is conducted with 60 partici‐ pants divided into 6 groups (2 modes×3 positions) using a tool that we developed to support the exploration of 3D visual structures in a collaborative manner. Our results show that the shared control and view version in the Side‐by‐Side position is the most favorable and can improve task efficiency. In this paper, we present the results and a set of recommendations that are derived from them

PAFSV: A Formal Framework for Specification and Analysis of SystemVerilog

We develop a process algebraic framework PAFSV for the formal specification and analysis of IEEE 1800TM SystemVerilog designs. The formal semantics of PAFSV is defined by means of deduction rules that associate a time transition system with a PAFSV process. A set of properties of PAFSV is presented for a notion of bisimilarity. PAFSV may be regarded as the formal language of a significant subset of IEEE 1800TM SystemVerilog. To show that PAFSV is useful for the formal specification and analysis of IEEE 1800TM SystemVerilog designs, we illustrate the use of PAFSV with a multiplexer, a synchronous reset D flip-flop and an arbiter

Porting LooCI Components into Zigduino

AbstractLoosely-coupled Component Infrastructure (LooCI) is a middleware for building distributed component-based WSN applications. LooCI cleanly separates distributed concerns from component implementation, supports application-level interoperability between heterogeneous WSN platforms, and provides compatibility testing of bindings at runtime.In this paper, we describe our approach to porting LooCI/Contiki from the Raven platform to the Zigduino platform, which is an Arduino-compatible microcontroller environmentthat integrates an 802.15.4 radio on the board